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Half Adder

Last updated Jun 23, 2022

# Half Adder

A circuit that adds two bits and outputs a carry and a bit of the sum is called Half Adder.
Sum is the XOR of $A$ and $B$, and the carry is the AND of $A$ and $B$, i.e. $$S = A \oplus B, \quad C = AB.$$
Code in Verilog:

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module halfadd(C,S,A,B); 
	input A, B; 
	output C, S; 
	
	xor xor1(S,A,B); 
	and and1(C,A,B); 
endmodule 

module main; 
	reg A,B; 
	wire C,S; 
	
	halfadd half1(C,S,A,B); 
	
	initial begin 
		A=0; 
		B=1; 
		#5; // Wait 5 time units. 
		$display("Carry = ",C); 
		$display("Sum = ",S); 
	end 
endmodule

# Sources

Chapter 1 - Classical Information and Computation > Half Adder

# Uses

Used in ripple-carry adder to perform binary addition.